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| HD74LS163A Synchronous 4-bit Binary Counter (direct clear) REJ03D0447-0200 Rev.2.00 Feb.18.2005 This synchronous 4-bit binary counter features an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This counter is fully programmable; that is, the output may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input would be avoided when the clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to LLLL. Low-to-high transitions at the clear input should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional getting. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low-level transitions at the enable P or T inputs should occur only when the clock input is high. Features * Ordering Information Part Name HD74LS163AP HD74LS163AFPEL HD74LS163ARPEL Package Type DILP-16 pin SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) PRSP0016DG-A (FP-16DNV) Package Abbreviation P FP RP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel) EL (2,500 pcs/reel) Note: Please consult the sales office for the above package availability. Rev.2.00, Feb.18.2005, page 1 of 11 HD74LS163A Pin Arrangement Clear Clock A Data Inputs B C D Enable P GND 1 2 3 4 5 6 7 8 CLR CK Ripple Carry A B C D P Load QA QB QC QD T 16 15 14 13 12 11 10 9 VCC Ripple Carry Output QA QB Outputs QC QD Enable T Load (Top view) Block Diagram Clock D Clear Load Enable P T A D CK B Q Q Output QB CK Q Q Output QA Data Inputs C DQ CK Q Output QC D DQ CK Q Output QD Ripple Carry Output Rev.2.00, Feb.18.2005, page 2 of 11 HD74LS163A Absolute Maximum Ratings Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Clock frequency Clock pulse width Clear pulse width A, B, C, D Setup time Enable P, T Load Clear Hold time th tsu Symbol VCC IOH IOL Topr clock tw (clock) tw (clear) Min 4.75 -- -- -20 0 25 20 20 20 20 20 3 Typ 5.00 -- -- 25 -- -- -- -- -- -- -- -- Max 5.25 -400 8 75 25 -- -- -- -- -- -- -- Unit V A mA C MHz ns ns ns ns ns ns ns Typical Clear, Preset, and Inhibit Sequence Clear Load A Data Inputs B C D Clock Enable P Enable T QA QB Outputs QC QD Carry 12 Clear Preset 13 14 15 0 Count 1 2 Inhibit Rev.2.00, Feb.18.2005, page 3 of 11 HD74LS163A Electrical Characteristics (Ta = -20 to +75 C) Item Input voltage Symbol VIH VIL VOH Output voltage VOL Data, Enable P Load, Clock, Enable T Clear Data, Enable P Load, Clock, Enable T Clear Data, Enable P Load, Clock, Enable T min. 2.0 -- 2.7 -- -- -- -- -- -- -- -- -- -- -- -20 -- typ.* -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18 max. -- 0.8 -- 0.4 0.5 20 40 40 -0.4 -0.8 -0.8 0.1 0.2 0.2 -100 31 Unit V V V V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, IOL = 8 mA VIL = 0.8 V VCC = 5.25 V, VI = 2.7 V IIH A Input current IIL mA VCC = 5.25 V, VI = 0.4 V II IOS ICCH mA mA mA VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V Clear Short-circuit output current Supply current** ICCL -- 19 32 mA VCC = 5.25 V Input clamp voltage VIK -- -- -1.5 V VCC = 4.75 V, IIN = -18 mA Notes: * VCC = 5 V, Ta = 25C ** ICC is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open. ICC is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open. Switching Characteristics (VCC = 5 V, Ta = 25C) Item Maximum clock frequency Symbol max tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Inputs Clock Clock Clock (Load = "H") Clock (Load = "L") Enable T Clear Outputs QA to QD Ripple Carry QA to QD QA to QD Ripple Carry QA to QD min. 25 -- -- -- -- -- -- -- -- -- typ. 32 20 18 13 18 13 18 9 9 20 max. -- 35 35 24 27 24 27 14 14 28 Unit MHz ns ns ns ns ns ns ns ns ns Condition Propagation delay time CL = 15 pF, RL = 2 k Rev.2.00, Feb.18.2005, page 4 of 11 HD74LS163A Timing Method tw (CK) 3V Clock 1.3V tsu Clear 1.3V th 3V 1.3V 1.3V tsu Load th 0V 3V 1.3V tsu Data Outputs A to D th 1.3V 0V 3V 1.3V 1.3V tsu Enable P or T 1.3V 1.3V 0V th 0V 3V 1.3V 1.3V 0V Testing Method Test Circuit VCC 4.5V Load circuit 1 QA Load CK Input A B C D RL QA CL See Testing Table P.G. Zout = 50 QB QB QC QC QD Ripple Carry Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Input P.G. Zout = 50 P T QD Ripple Carry CLR Notes: 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Rev.2.00, Feb.18.2005, page 5 of 11 HD74LS163A Testing Table Item max CK Ripply Carry CK Q CK Q Enable T CLR Q Ripple Carry From input to output Inputs Clear 4.5V 4.5V 4.5V 4.5V 4.5V IN Load 4.5V 4.5V 4.5V GND GND GND Enable P 4.5V 4.5V 4.5V GND 4.5V GND T 4.5V 4.5V 4.5V GND IN GND Clock IN IN IN IN IN* IN* Data A GND GND GND IN* 4.5V 4.5V B GND GND GND IN* 4.5V 4.5V C GND GND GND IN* 4.5V 4.5V D GND GND GND IN* 4.5V 4.5V tPLH tPHL Notes: *. For initialized Outputs QA OUT -- OUT OUT -- OUT QB OUT -- OUT OUT -- OUT QC OUT -- OUT OUT -- OUT QD OUT -- OUT OUT -- OUT Ripple Carry OUT OUT -- -- OUT -- Item max From input to output tPLH tPHL CKRipple Carry CKQ CKQ Enable TRipple Carry CLRQ Rev.2.00, Feb.18.2005, page 6 of 11 HD74LS163A Waveforms 1 max, tPLH, tPHL, (ClockQ, Ripple Carry) tTLH tTHL 3V 1.3V tPHL (Measure at tn + 2) 1.3V tPHL tPLH (Measure at tn + 2) (Measure at tn + 4) QB 1.3V 1.3V VOL tPLH (Measure at tn + 4) tPHL (Measure at tn + 8) QC 1.3V tPHL (Measure at tn + 16) QD tPLH (Measure at tn + 15) Ripple Carry 1.3V 1.3V tPHL (Measure at tn + 16) VOH 1.3V VOL 1.3V VOL tPLH (Measure at tn + 8) VOH 1.3V VOL VOH VOL VOH 1.3V 0V VOH 1.3V Clock 10% 90% 90% 1.3V 1.3V 10% (Measure at tn + 1) tw (CK) tPLH QA Note: Clock input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz, duty cycle 50% and : max tTLH = tTHL 2.5 ns. tn is reference bit time when all outputs are low. Rev.2.00, Feb.18.2005, page 7 of 11 HD74LS163A Waveforms 2 tPLH, tPHL, (ClockQ) tTLH 90% Clock 10% tTLH tTHL 90% 1.3V 10% tTHL 90% Data Inputs A, B, C or D 10% tPLH Outputs QA, QB, QC or QD 90% 10% tPHL VOH 1.3V 1.3V VOL 3V 1.3V 0V 3V 0V Note: Input pulse: tTLH 15 ns, tTHL 6 ns, Clock input: PRR = 1 MHz, duty cycle 50%, Data input: PRR = 500 kHz, duty cycle 50% Waveforms 3 tPLH, tPHL, (Enable TRipple Carry) tTLH 90 % 1.3 V 10 % tPLH tTHL 90 % 1.3 V 10 % tPHL 3V 0V Enable T VOH Ripple Carry 1.3 V 1.3 V VOH Note: Input pulse: tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz Rev.2.00, Feb.18.2005, page 8 of 11 HD74LS163A Waveforms 4 tPHL, (ClearQ) tTLH 90% Clock 10% tTHL 90% 1.3V 10% tPHL VOH QA to QD 1.3V VOL tTHL 90% 1.3V 10% tw (CLR) 20ns tTLH 90% 1.3V 10% 0V 3V 3V Clear 0V Note: Input pulse: tTLH 15 ns, tTHL 6 ns Rev.2.00, Feb.18.2005, page 9 of 11 HD74LS163A Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 16 9 1 0.89 b3 8 Z E A1 A Reference Symbol Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max e D E L 1 A A1 e bp e1 b c b c p 3 e Z ( Ni/Pd/Au plating ) L JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g *1 D F 9 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp HE E Index mark Reference Symbol *2 c Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5 Terminal cross section ( Ni/Pd/Au plating ) 1 Z e *3 D E A2 8 bp x M L1 A1 A bp b1 c 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 1 0.20 0.25 A c HE 0 7.50 7.80 1.27 8 8.00 A1 y L e x y 0.12 0.15 0.80 0.50 1 Detail F Z L L 0.70 1.15 0.90 Rev.2.00, Feb.18.2005, page 10 of 11 HD74LS163A JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A Previous Code FP-16DNV MASS[Typ.] 0.15g *1 D 9 F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp Index mark *2 E HE c Reference Symbol Dimension in Millimeters Min Nom 9.90 3.95 Max 10.30 Terminal cross section ( Ni/Pd/Au plating ) 1 Z e *3 D E A2 8 bp x M L1 A1 A bp b1 c c 1 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 HE 0 5.80 6.10 1.27 8 6.20 A A1 L y e x y 0.25 0.15 0.635 0.40 1 Detail F Z L L 0.60 1.08 1.27 Rev.2.00, Feb.18.2005, page 11 of 11 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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